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<body class='hmmessage'><div dir='ltr'>ps: in the "read 4 byte proposal", there'd still be an entire integer there, we just wouldn't bother checking the entire thing. That way, we'd only require 4 alignment, which is how instructions/functions are always aligned on everything but arm32 and x86 and amd64. This seems fairly elegant, but maybe a new target would break it.<div>i.e. it is clear that the ideal design has a fixed size instruction, of probably 4 bytes.</div><div><br></div><div>Almost every architecture looks like that -- mips, alpha, powerpc, sparc, arm64, I think happier.</div><div>But there is the unfortunate x86 design with anything from 1 to 15 byte instruction, and the unfortunate arm32 design with 2 or 4 byte instructions, 2 byte instructions being indicated by having an odd address.</div><div><br></div><div><br></div><div> - Jay<br><br><br><div><hr id="stopSpelling">From: jay.krell@cornell.edu<br>To: hosking@purdue.edu<br>Date: Mon, 21 Sep 2015 02:57:21 +0000<br>CC: m3commit@elegosoft.com<br>Subject: Re: [M3commit] [modula3/cm3] ced183: Aligned_procedures always FALSE -- reduce target v...<br><br>
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<div dir="ltr">I didn't change the alignment of anything.<div><br></div><div><br></div><div>At a level we do not control, the alignment on NT/amd64 I believe is 4 when optimizing for space, 16 when optimizing for speed. Any alignment works, but this is what you will see in practice.</div><div>I don't believe you will see 8-alignment, except typically half of the size-aligned functions that are 4-aligned.</div><div>Probably all amd64 targets are like this but I'd have to check.</div><div><br></div><div><br></div><div>But we don't control this and I didn't change it.</div><div><br></div><div><br></div><div>The alignment on NT of heap allocation is two pointers.</div><div>The alignment of closures in Modula-3 is presumably at least pointer.</div><div><br></div><div><br></div><div>What this does is affect the alignment check of a closure.</div><div>On x86/amd64, we can safely read 4 or 8 bytes from any pointer, and compare for -1.</div><div>No alignment check is needed.</div><div>On other architectures, the reads need to be aligned.</div><div><br></div><div><br></div><div>What the code does, optionally, is check the alignment, and if it isn't integer-aligned,</div><div>it is assumed to be code, not a closure, and the check for -1 is skipped.</div><div><br></div><div><br></div><div>What the change does is add the alignment check for all architectures.</div><div>Previously it was only present for 64 bit architectures, except amd64.</div><div><br></div><div><br></div><div>Another proposal is to always clear the lower 2 bits and check for a 4 byte -1.</div><div>The conditional branch would be gone.</div><div>The clearing of the lower 2 bits is only to accommodate ARM32.</div><div>On everything but ARM32, either alignment doesn't matter (x86/amd64) or all instructions/functions</div><div>are at least 4-aligned. Doing an 8-byte check is redundant, and risks an alignment fault.</div><div><br></div><div><br></div><div> - Jay<br><br><br><div><hr id="ecxstopSpelling">Subject: Re: [M3commit] [modula3/cm3] ced183: Aligned_procedures always FALSE -- reduce target v...<br>From: hosking@purdue.edu<br>Date: Mon, 21 Sep 2015 12:48:09 +1000<br>CC: m3commit@elegosoft.com<br>To: jay.krell@cornell.edu<br><br><div>It's my understanding that 8-byte procedure alignment performs better on x86-64. <br><br>Sent from my iPhone</div><div><br>On Sep 21, 2015, at 12:21 PM, Jay K <<a href="mailto:jay.krell@cornell.edu">jay.krell@cornell.edu</a>> wrote:<br><br></div><blockquote><div>
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<div dir="ltr">I don't think so. Calls through function pointers will incur like two extra instructions, an and and a conditional branch. All 32bit targets in fact will pay that cost, and only arm32 needs it.<div><br></div><div><br></div><div>I have another propose a week or so go, roughly, for all targets:</div><div> mask off lower two bits </div><div> only read 4 bytes </div><div><br></div><div> </div><div>That would avoid the conditional branch.</div><div>It should work for all targets also.</div><div>The masking is only needed for ARM32.</div><div>All other targets have either 4-byte aligned instructions, or don't care about alignment faults.</div><div><br></div><div><br></div><div> - Jay<br><br><br><br><div>> Subject: Re: [M3commit] [modula3/cm3] ced183: Aligned_procedures always FALSE -- reduce target v...<br>> From: <a href="mailto:hosking@purdue.edu">hosking@purdue.edu</a><br>> Date: Mon, 21 Sep 2015 10:47:05 +1000<br>> CC: <a href="mailto:m3commit@elegosoft.com">m3commit@elegosoft.com</a><br>> To: <a href="mailto:jay.krell@cornell.edu">jay.krell@cornell.edu</a><br>> <br>> This will break some targets I believe. X86/x86-64 no?<br>> <br>> Sent from my iPhone<br>> <br>> > On Sep 21, 2015, at 2:43 AM, jaykrell <<a href="mailto:jay.krell@cornell.edu">jay.krell@cornell.edu</a>> wrote:<br>> > <br>> > Branch: refs/heads/master<br>> > Home: <a href="https://github.com/modula3/cm3" target="_blank">https://github.com/modula3/cm3</a><br>> > Commit: ced183d086a829001f44ea5f8f791df2e3952d4f<br>> > <a href="https://github.com/modula3/cm3/commit/ced183d086a829001f44ea5f8f791df2e3952d4f" target="_blank">https://github.com/modula3/cm3/commit/ced183d086a829001f44ea5f8f791df2e3952d4f</a><br>> > Author: jaykrell <<a href="mailto:jay.krell@cornell.edu">jay.krell@cornell.edu</a>><br>> > Date: 2015-09-20 (Sun, 20 Sep 2015)<br>> > <br>> > Changed paths:<br>> > M m3-sys/m3middle/src/Target.m3<br>> > <br>> > Log Message:<br>> > -----------<br>> > Aligned_procedures always FALSE -- reduce target variation<br>> > <br>> > <br>> > _______________________________________________<br>> > M3commit mailing list<br>> > <a href="mailto:M3commit@elegosoft.com">M3commit@elegosoft.com</a><br>> > <a href="https://mail.elegosoft.com/cgi-bin/mailman/listinfo/m3commit" target="_blank">https://mail.elegosoft.com/cgi-bin/mailman/listinfo/m3commit</a><br></div></div> </div>
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