<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div>Here is my updated proposal for Modula-3 Atomic Word.T.</div><div>These are based on what we can have implemented from libatomic_ops, a prototype implementation for the C++ memory model standardization process. At the moment they are not gcc intrinsics, but I expect to see that coming as the standard progresses.</div><div><br></div><div><div>INTERFACE Atomic;</div><div><br></div><div>IMPORT Word;</div><div><br></div><div>TYPE T = Word.T;</div><div><br></div><div>TYPE</div><div> Order = { Relaxed, Release, Acquire, AcquireRelease, Sequential };</div><div> (* "Relaxed": The operation does not order memory.</div><div><br></div><div> "Release": Performs a release operation on the affected memory locations,</div><div> thus making regular memory writes visible to other threads through the</div><div> variable to which it is applied.</div><div><br></div><div> "Acquire": Performs an acquire operation on the affected memory</div><div> locations, thus making regular memory writes in other threads released</div><div> through the atomic variable to which it is applied, visible to the</div><div> current thread.</div><div><br></div><div> "AcquireRelease": The operation has both acquire and release semantics.</div><div><br></div><div> "Sequential": The operation has both acquire and release semantics, and</div><div> in addition, has sequentially-consistent operation ordering. *)</div><div><br></div><div>CONST IsLockFree = RTMachine.IsLockFree;</div><div> (* True if the operations are lock-free, false otherwise. *)</div><div><br></div><div>PROCEDURE Store(VAR var: T; val: T; order := Order.Sequential);</div><div> (* Atomically replace the value in "var" with "val". Memory is affected as</div><div> per "order". The "order" shall be neither "Acquire" nor</div><div> "AcquireRelease". *)</div><div><br></div><div>PROCEDURE Load(READONLY var: T; order := Order.Sequential): T;</div><div> (* Atomically return the value in "var". Memory is affected as per "order".</div><div> The "order" shall be neither "Release" nor "AcquireRelease". *)</div><div><br></div><div>PROCEDURE Swap(VAR var: T; val: T; order := Order.Sequential): T;</div><div> (* Atomically replace the value in "var" with "val". Returns the value of</div><div> "var" immediately before the effects. Memory is affected as per order.</div><div> This is a read-modify-write operation and synchronizes with any</div><div> evaluation that reads the updated value. *)</div><div><br></div><div>PROCEDURE CompareSwap(VAR var, expected: T;</div><div> desired: T; order := Order.Sequential): BOOLEAN;</div><div> (* Atomically, compares the value in "var" for equality with that in</div><div> "expected", and if true, replaces the value in "var" with "desired", and</div><div> if false, updates the value in "expected" with the value in "var".</div><div> Returns the result of the comparison. The "order" shall be neither</div><div> "Release" nor "AcquireRelease". This is a read-modify-write operation</div><div> and synchronizes with any evaluation that reads the updated value. The</div><div> effect of the CompareSwap operation is:</div><div><br></div><div> IF var = expected THEN var := desired ELSE expected := var;</div><div><br></div><div> The CompareSwap operation may fail spuriously, that is return false while</div><div> leaving the value in "expected" unchanged. A consequence of spurious</div><div> failure is that nearly all uses of CompareSwap will be in a loop:</div><div><br></div><div> expected := Atomic.Load(current);</div><div> DO</div><div> desired := function(expected);</div><div> WHILE NOT Atomic.CompareSwap(current, expected, desired);</div><div> *)</div><div><br></div><div>PROCEDURE Fence(VAR var: T; order := Order.Sequential);</div><div> (* Memory is affected as per "order". Synchronizes with any operation on</div><div> the same variable. The "order" shall not be "Relaxed". *)</div><div><br></div><div>PROCEDURE FetchPlus (VAR var; incr: T; order := Sequential): T;</div><div>PROCEDURE FetchMinus(VAR var; mask: T; order := Sequential): T;</div><div>PROCEDURE FetchOr (VAR var; mask: T; order := Sequential): T;</div><div>PROCEDURE FetchXOr (VAR var; mask: T; order := Sequential): T;</div><div>PROCEDURE FetchXAnd (VAR var; mask: T; order := Sequential): T;</div><div> (* Atomically replace the value in "var" with the result of the operation</div><div> applied to the value in "var" and the given operand. Memory is affected</div><div> as per "order". These operations are read-modify-write operations and</div><div> synchronize with any evaluation that reads the updated value. Returns</div><div> the value of "var" immediately before the effects.</div><div><br></div><div> For signed integral types, arithmetic is defined to use two's-complement</div><div> representation. There are no undefined results. For address types, the</div><div> result may be an undefined address, but the operations otherwise have no</div><div> undefined behavior. *)</div><div><br></div><div>END Atomic.</div><div><br></div></div><br><div>
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