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There should be a link to the C++ proposal?<BR>
<BR>
As well, new idea, I like the idea of source files<BR>
containing a link to their cvsweb page.<BR>
Not to the specific version, but something fairly "stable".<BR>
<BR>
- Jay<BR><BR> <BR>
<HR id=stopSpelling>
From: hosking@cs.purdue.edu<BR>Date: Sat, 19 Dec 2009 18:35:31 -0500<BR>To: hosking@cs.purdue.edu<BR>CC: m3devel@elegosoft.com<BR>Subject: Re: [M3devel] Proposed Atomic Word.T interfaces.<BR><BR>
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<DIV><FONT class=ecxApple-style-span color=#0000ff face="'Gill Sans'"><SPAN style="FONT-SIZE: medium" class=ecxApple-style-span>Typo: FetchXAnd should read FetchAnd.</SPAN></FONT></DIV></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></DIV></SPAN></SPAN></DIV><BR>
<DIV>
<DIV>On 19 Dec 2009, at 18:30, Tony Hosking wrote:</DIV><BR class=ecxApple-interchange-newline>
<BLOCKQUOTE>
<DIV style="WORD-WRAP: break-word">
<DIV>Here is my updated proposal for Modula-3 Atomic Word.T.</DIV>
<DIV>These are based on what we can have implemented from libatomic_ops, a prototype implementation for the C++ memory model standardization process. At the moment they are not gcc intrinsics, but I expect to see that coming as the standard progresses.</DIV>
<DIV><BR></DIV>
<DIV>
<DIV>INTERFACE Atomic;</DIV>
<DIV><BR></DIV>
<DIV>IMPORT Word;</DIV>
<DIV><BR></DIV>
<DIV>TYPE T = Word.T;</DIV>
<DIV><BR></DIV>
<DIV>TYPE</DIV>
<DIV> Order = { Relaxed, Release, Acquire, AcquireRelease, Sequential };</DIV>
<DIV> (* "Relaxed": The operation does not order memory.</DIV>
<DIV><BR></DIV>
<DIV> "Release": Performs a release operation on the affected memory locations,</DIV>
<DIV> thus making regular memory writes visible to other threads through the</DIV>
<DIV> variable to which it is applied.</DIV>
<DIV><BR></DIV>
<DIV> "Acquire": Performs an acquire operation on the affected memory</DIV>
<DIV> locations, thus making regular memory writes in other threads released</DIV>
<DIV> through the atomic variable to which it is applied, visible to the</DIV>
<DIV> current thread.</DIV>
<DIV><BR></DIV>
<DIV> "AcquireRelease": The operation has both acquire and release semantics.</DIV>
<DIV><BR></DIV>
<DIV> "Sequential": The operation has both acquire and release semantics, and</DIV>
<DIV> in addition, has sequentially-consistent operation ordering. *)</DIV>
<DIV><BR></DIV>
<DIV>CONST IsLockFree = RTMachine.IsLockFree;</DIV>
<DIV> (* True if the operations are lock-free, false otherwise. *)</DIV>
<DIV><BR></DIV>
<DIV>PROCEDURE Store(VAR var: T; val: T; order := Order.Sequential);</DIV>
<DIV> (* Atomically replace the value in "var" with "val". Memory is affected as</DIV>
<DIV> per "order". The "order" shall be neither "Acquire" nor</DIV>
<DIV> "AcquireRelease". *)</DIV>
<DIV><BR></DIV>
<DIV>PROCEDURE Load(READONLY var: T; order := Order.Sequential): T;</DIV>
<DIV> (* Atomically return the value in "var". Memory is affected as per "order".</DIV>
<DIV> The "order" shall be neither "Release" nor "AcquireRelease". *)</DIV>
<DIV><BR></DIV>
<DIV>PROCEDURE Swap(VAR var: T; val: T; order := Order.Sequential): T;</DIV>
<DIV> (* Atomically replace the value in "var" with "val". Returns the value of</DIV>
<DIV> "var" immediately before the effects. Memory is affected as per order.</DIV>
<DIV> This is a read-modify-write operation and synchronizes with any</DIV>
<DIV> evaluation that reads the updated value. *)</DIV>
<DIV><BR></DIV>
<DIV>PROCEDURE CompareSwap(VAR var, expected: T;</DIV>
<DIV> desired: T; order := Order.Sequential): BOOLEAN;</DIV>
<DIV> (* Atomically, compares the value in "var" for equality with that in</DIV>
<DIV> "expected", and if true, replaces the value in "var" with "desired", and</DIV>
<DIV> if false, updates the value in "expected" with the value in "var".</DIV>
<DIV> Returns the result of the comparison. The "order" shall be neither</DIV>
<DIV> "Release" nor "AcquireRelease". This is a read-modify-write operation</DIV>
<DIV> and synchronizes with any evaluation that reads the updated value. The</DIV>
<DIV> effect of the CompareSwap operation is:</DIV>
<DIV><BR></DIV>
<DIV> IF var = expected THEN var := desired ELSE expected := var;</DIV>
<DIV><BR></DIV>
<DIV> The CompareSwap operation may fail spuriously, that is return false while</DIV>
<DIV> leaving the value in "expected" unchanged. A consequence of spurious</DIV>
<DIV> failure is that nearly all uses of CompareSwap will be in a loop:</DIV>
<DIV><BR></DIV>
<DIV> expected := Atomic.Load(current);</DIV>
<DIV> DO</DIV>
<DIV> desired := function(expected);</DIV>
<DIV> WHILE NOT Atomic.CompareSwap(current, expected, desired);</DIV>
<DIV> *)</DIV>
<DIV><BR></DIV>
<DIV>PROCEDURE Fence(VAR var: T; order := Order.Sequential);</DIV>
<DIV> (* Memory is affected as per "order". Synchronizes with any operation on</DIV>
<DIV> the same variable. The "order" shall not be "Relaxed". *)</DIV>
<DIV><BR></DIV>
<DIV>PROCEDURE FetchPlus (VAR var; incr: T; order := Sequential): T;</DIV>
<DIV>PROCEDURE FetchMinus(VAR var; mask: T; order := Sequential): T;</DIV>
<DIV>PROCEDURE FetchOr (VAR var; mask: T; order := Sequential): T;</DIV>
<DIV>PROCEDURE FetchXOr (VAR var; mask: T; order := Sequential): T;</DIV>
<DIV>PROCEDURE FetchXAnd (VAR var; mask: T; order := Sequential): T;</DIV>
<DIV> (* Atomically replace the value in "var" with the result of the operation</DIV>
<DIV> applied to the value in "var" and the given operand. Memory is affected</DIV>
<DIV> as per "order". These operations are read-modify-write operations and</DIV>
<DIV> synchronize with any evaluation that reads the updated value. Returns</DIV>
<DIV> the value of "var" immediately before the effects.</DIV>
<DIV><BR></DIV>
<DIV> For signed integral types, arithmetic is defined to use two's-complement</DIV>
<DIV> representation. There are no undefined results. For address types, the</DIV>
<DIV> result may be an undefined address, but the operations otherwise have no</DIV>
<DIV> undefined behavior. *)</DIV>
<DIV><BR></DIV>
<DIV>END Atomic.</DIV>
<DIV><BR></DIV></DIV><BR>
<DIV><SPAN style="FONT-SIZE: 12px" class=ecxApple-style-span>
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