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yes, but I think it is target-specific. IA64 would use 16 bytes.<BR>
It isn't even in library code, but generated code.<BR>
 <BR>
 - Jay<BR><BR> <BR>
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From: hosking@cs.purdue.edu<BR>Date: Wed, 27 Jan 2010 10:57:09 -0500<BR>To: jay.krell@cornell.edu<BR>CC: m3devel@elegosoft.com<BR>Subject: Re: [M3devel] aligned_procedures: suggest "closure_marker_size"<BR><BR><BASE>If we declare it as a 32-bit subrange it should just work, right?
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<DIV>On 27 Jan 2010, at 09:01, Jay K wrote:</DIV><BR class=ecxApple-interchange-newline>
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<DIV style="FONT-FAMILY: Verdana; FONT-SIZE: 10pt" class=ecxhmmessage>MIPS64, SPARC64 and maybe others could probably all benefit slightly from<BR>  the closure marker being a 4 byte -1 instead of an INTEGER.<BR> <BR> <BR> That is: 64bit architectures with a fixed size 4 byte instruction where alignment is checked<BR><BR> <BR> That is, we should probably make their be a per-target variable "closure marker size"<BR>  that is 4 for all current targets (IA64 should probably be 16 though),<BR>  though one would have to look into the various instruction encodings.<BR><BR><BR> - Jay<BR></DIV></SPAN></BLOCKQUOTE></DIV><BR></DIV>                                    </body>
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