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<pre> > packing data into record about packing bits left-right-until-spent?</pre><br>It is not portable.<br>In particular, there is endianness variation.<br>The C spec leaves things up to implementation.<br><br>If you can, I recommend copying the data from C to a more portable less dense Modula-3 representation.<br>Like what is now done throughout m3core/libm3 -- i.e. we don't interface with C at all through bitfields, nor do we try to line up with struct stat or any other struct, roughly speaking.<br>(Maybe still a few, like struct linger).<br><br><br> - Jay<br><br><br><div><div id="SkyDrivePlaceholder"></div>> From: dragisha@m3w.org<br>> Date: Wed, 18 Jan 2012 15:10:31 +0100<br>> To: m3devel@elegosoft.com<br>> Subject: [M3devel] packing problem… how exactly does modula-3 pack data into records??<br>> <br>> As per subject… I would like to pack this:<br>> <br>> TSPacketHeader = RECORD<br>> sync: BITS 8 FOR File.Byte; (* Always 0x47 *)<br>> tErrInd, (* Transport Error Indicator *)<br>> pusi: BITS 1 FOR BOOLEAN; (* Payload Unit Start Indicator *)<br>> transPrio: BITS 1 FOR [0..1];<br>> pid: BITS 13 FOR PID;<br>> transScramControl: BITS 2 FOR [0..3]; (* 00 means no scrambling *)<br>> afc: BITS 2 FOR [0..3]; (* 01 - no adaptation field, payload only *)<br>> cc: BITS 4 FOR Nibble;<br>> END;<br>> <br>> My data, pusi is TRUE, sync is 0x47, pid is 4129 (0x1021), cc is 5 and afc is 0x1.Rest is zeros.<br>> <br>> What I get is:<br>> <br>> 0000 1010 1000 0001 0101 0100<br>> <br>> last five bits of pid; one bit for transPrio, one bit for pusi (TRUE), one bit for tErrInd;<br>> first eight bits of pid<br>> four bits of cc; two bits of abc; two bits for transScramControl<br>> <br>> a mess. with pid being most special sort of it :).<br>> <br>> Is this excected/normal? Wasn't whole idea os packing data into record about packing bits left-right-until-spent?<br>> <br>> TIA,<br>> dd<br>> <br></div> </div></body>
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