<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Single "execution space" can span over various architectures in few ways. Examples - RPC and GPU.<div><div><br></div><div>RPC is nothing new and it does not presume multi architecture for single object file. Nor it presumes single address space for various components/processes. There is cross-process boundary where conversions (data marshaling/unmarshalling) happen. <div><br></div><div>On the other hand, GPU programming… No cross-process boundary in RPC style, it almost looks like it is single executable - but it is not "multiple CPU architecture per single object". Nor does it include single address space for various object components included.</div><div><br></div><div>GPU is an excellent example of what you are, very obliquely, hinting at. But - it is not single object file for multiple architectures for single address space. </div><div><br></div><div>It is probably good idea for you to look at GPU's today to see what is realistic in multi-architecture object generation/application.</div><div><div><br><div><div>On Apr 25, 2012, at 9:24 PM, Daniel Alejandro Benavides D. wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><table cellspacing="0" cellpadding="0" border="0"><tbody><tr><td valign="top" style="font: inherit;">Hi all:<br>Such as a module generating code, for sending both LONGINTs and LONGADDRESSes through networks of wide processing units MCU (e.g array processors)?<br><a href="http://books.google.com.co/books?id=oM4EAQAAIAAJ&q=%22Address+register+2%22#search_anchor">http://books.google.com.co/books?id=oM4EAQAAIAAJ&q=%22Address+register+2%22#search_anchor</a><br><br>http://books.google.com.co/books?id=oM4EAQAAIAAJ&q=74ACT8847#search_anchor<br><br>I guess I should tell you one, but there are too many to count examples, in any case you would want to be truly multi platform and cross-porting easier in general, rather than based in one base case, though Modula was too good to make such things difficult in any case. If it serves to know multitasking of DEC has been emulated through the AMD Bulldozer microarchitecture with Array/Vector processor, etc. But it still needs more cooperation (or at least using shared standards) on the industry to return to those
good days.<br><br>Thanks in advance <br><br>--- El <b>mié, 25/4/12, felipe valdez <i><dataf4l@gmail.com></i></b> escribió:<br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px;"><br>De: felipe valdez <dataf4l@gmail.com><br>Asunto: Re: [M3devel] LONGADDRESS [was: Re: Downsides of Modula-3 ?]<br>Para: "Dragiša Durić" <dragisha@m3w.org><br>CC: "Daniel Alejandro Benavides D." <dabenavidesd@yahoo.es>, m3devel@elegosoft.com<br>Fecha: miércoles, 25 de abril, 2012 11:08<br><br><div id="yiv1191190458"><div class="yiv1191190458gmail_extra">that is quite a response.</div><div class="yiv1191190458gmail_extra"><br><br><div class="yiv1191190458gmail_quote">On Wed, Apr 25, 2012 at 8:08 AM, Dragiša Durić <span dir="ltr"><<a rel="nofollow" ymailto="mailto:dragisha@m3w.org" target="_blank" href="x-msg://1456/mc/compose?to=dragisha@m3w.org">dragisha@m3w.org</a>></span> wrote:<br>
<blockquote class="yiv1191190458gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"><div style="">As my first hands-on CPU was 6502, I think I remember a lot.<div><br></div><div>ADDRESS is pointer size, and even C world spins around one pointer size per architecture. Of course there are various architectures, with their various specifics. Not only pointer size, of course. </div>
<div><br></div><div>What use would be to have two pointer sizes in single project? Do you expect one thread of your program to run on one CPU, second thread on another, different CPU?</div><div><br></div><div><div><div><div>
On Apr 24, 2012, at 4:42 PM, Daniel Alejandro Benavides D. wrote:</div><br><blockquote type="cite"><span style="border-collapse: separate; font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; font-size: medium;">Hi all:<br>
All the contrary Dragisha, do you remember the Micro's era 6809, 4004, etc, so then it became gradually 68000, 8088 - 80186, etc.<br>So we can see in ARM versions, but now, probably in AMD64, that they are planning the next step, as were the same histories for those days.<br>
We could use it like for porting 32 bit backend to 64 bit painfully less stressful, I mean, even the OS/400 has this feature of 128 pointers to allow updating architecture, without language change.<br><br>So I'd guess is rather cross-portability, upwards and that's it. Of course this would require more TYPE declarations and VAR as well (LADR, LVAR), but could be less painful for the ones who want to port to that.<br>
It must be done carefully aggressively because this is a changing world, what can I say? <br>Thanks in advance</span></blockquote></div><br></div></div></div></blockquote></div><br><br clear="all"><br>-- <br><div>312-444-2124<div>
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