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<body class='hmmessage'><div dir='ltr'>I forgot to mention/ask: "packed" basically means "no padding", right?<BR> <BR> - Jay<br><br> <BR><div><hr id="stopSpelling">From: jay.krell@cornell.edu<br>To: lists@darko.org; rodney_bates@lcwb.coop<br>Date: Sun, 27 Sep 2015 05:17:14 +0000<br>CC: m3devel@elegosoft.com<br>Subject: Re: [M3devel] Another Allow_packed_byte_aligned issue<br><br>
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<div dir="ltr">I agree it is probably messed up, but I wonder if another approach or approaches can/should be taken.<div><br></div><div>1)</div><div><br></div><div>I wonder if the boolean should be true for all targets.</div><div>And the pragmas removed, or changed to do nothing.</div><div><br></div><div>And, here comes the important part:</div><div> for any unaligned load/store, m3front break it down into multiple smaller loads/stores</div><div><br></div><div><br></div><div>Upsides:</div><div> same predictable layout for all targets</div><div> same does-it-compile/does-it-not-compile behavior for all targets</div><div><br></div><div>Downsides:</div><div> possibly atomic accesses are no longer atomic</div><div> possibly "efficient" accesses are no longer atomic.</div><div><br></div><div>2)</div><div>Similar to before:</div><div> allow same layouts on all architecures</div><div><br></div><div>but on architectures where alignment doesn't matter much, just do the unaligned loads/stores</div><div><br></div><div>Keep in mind that "interlocked" alignment does reportedly matter on x86 -- x86 is not really entirely alignment-agnostic.</div><div>I believe alignment of avx loads/stores sometimes matters too -- again, x86 does care sometimes.</div><div><br></div><div>And the rules are more complicated than m3front/m3middle can encode.</div><div><br></div><div>Not that we have any avx data types.</div><div>I'd have to experiment more on the sse2 stuff which we do presumably use.</div><div><br></div><div>And yes I agree it generates alignment faults on some targets.</div><div>We should be able to reproduce this easily enough e.g. on SPARC.</div><div><br></div><div>(Not to mention that x86 can be asked to take alignment faults...it is a mode bit in the processor, that just</div><div>tends to be off.)</div><div><br></div><div> - Jay<br><br><br><div><hr id="ecxstopSpelling">Date: Sat, 26 Sep 2015 18:27:59 -0700<br>From: lists@darko.org<br>To: rodney_bates@lcwb.coop<br>CC: m3devel@elegosoft.com<br>Subject: Re: [M3devel] Another Allow_packed_byte_aligned issue<br><br><div dir="ltr"><span style="font-family: Arial,sans-serif; font-size: 13.33px;">I implemented the byte aligned packing functionality and the Allow_packed_byte_</span><span style="font-family: Arial,sans-serif; font-size: 13.33px;">aligned flag was supposed to be a constant that signified that the target CPU allows byte alignment thus relaxing the normal packing restrictions.</span><br><div><span style="font-family: Arial,sans-serif; font-size: 13.33px;"><br></span></div><div><font face="Arial, sans-serif"><span style="font-size: 13.33px;">I can't speak for the implementation of the pragma (or later changes), but I think it should be removed since (in my mind) it doesn't serve any useful purpose.</span></font></div><div><font face="Arial, sans-serif"><span style="font-size: 13.33px;"><br></span></font></div></div><div class="ecxgmail_extra"><br><div class="ecxgmail_quote">On Sat, Sep 26, 2015 at 12:23 PM, Rodney Bates <span dir="ltr"><<a href="mailto:rodney_bates@lcwb.coop" target="_blank">rodney_bates@lcwb.coop</a>></span> wrote:<br><blockquote class="ecxgmail_quote" style="padding-left: 1ex; border-left-color: rgb(204, 204, 204); border-left-width: 1px; border-left-style: solid;"><div style="font-family: Arial,sans-serif; font-size: 10pt;">In trying to better understand the issue, I see, in Module.m3:895, this code:<br><br> Target.Allow_packed_byte_aligned := t.containsLazyAlignments;<br><br>From other places, containsLazyAlignments derives from LAZYALIGN <br>pragmas, so this means it will turn on Allow_packed_byte_aligned,<br>regardless of the target, if there is a LAZYALIGN pragma. I think this<br>will generate code that will alignfault, if the target CPU doesn't<br>support it. That would be a bug. <br><span class="ecxHOEnZb"><font color="#888888"><br><br>-Rodney Bates</font></span></div>
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