[M3devel] I know, I know...

[Dragiša Durić]

I know this will probably be very dense subject, but… What about:

  TSPacketHeader = <* ENDIAN = BIG*>RECORD
    sync: BITS 8 FOR [16_0..16_ff];   (* Always 0x47 *)
    tErrInd,                      (* Transport Error Indicator *)
    pusi: BITS 1 FOR BOOLEAN;     (* Payload Unit Start Indicator *)
    transPrio: BITS 1 FOR [0..1];
    pid: BITS 13 FOR PID;
    transScramControl: BITS 2 FOR [0..3]; (* 00 means no scrambling *)
    afc: BITS 2 FOR [0..3]; (* 01 - no adaptation field, payload only *) 
    cc: BITS 4 FOR Nibble;
  END;

Meaning: bit data is packed from left to right, and all multi-byte data is packed MSB first.

Right now I am doing this, based on knowledge of my platform (little endian, x86_64), like this:

  TSPacketHeader = RECORD
    sync: BITS 8 FOR [16_0..16_ff];   (* Always 0x47 *)
    
    pidHi: BITS 5 FOR [16_00..16_1f];
    transPrio: BITS 1 FOR [0..1];
    pusi,
    tErrInd: BITS 1 FOR BOOLEAN;
    
    pidLo: BITS 8 FOR [16_00..16_ff];
    
    cc: BITS 4 FOR Nibble;
    afc: BITS 2 FOR [0..3]; (* 01 - no adaptation field, payload only *) 
    transScramControl: BITS 2 FOR [0..3]; (* 00 means no scrambling *)
  END;

And please don't tell me "write in C", because then I will just "offload" this problem to C preprocessor and still only hope for the best. Modula-3 is provably very adept to systems programming and I hope it can be more so.

Thanks in advance..
--
Divided by a common language

Dragiša Durić
dragisha at m3w.org




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