[M3devel] packing problem… how exactly does modula-3 pack data into records??

[Jay K]

 > packing data into record about packing bits left-right-until-spent?
It is not portable.
In particular, there is endianness variation.
The C spec leaves things up to implementation.

If you can, I recommend copying the data from C to a more portable less dense Modula-3 representation.
Like what is now done throughout m3core/libm3 -- i.e. we don't interface with C at all through bitfields, nor do we try to line up with struct stat or any other struct, roughly speaking.
(Maybe still a few, like struct linger).


 - Jay


> From: dragisha at m3w.org
> Date: Wed, 18 Jan 2012 15:10:31 +0100
> To: m3devel at elegosoft.com
> Subject: [M3devel] packing problem… how exactly does modula-3 pack data into records??
> 
> As per subject… I would like to pack this:
> 
>   TSPacketHeader = RECORD
>     sync: BITS 8 FOR File.Byte;   (* Always 0x47 *)
>     tErrInd,                      (* Transport Error Indicator *)
>     pusi: BITS 1 FOR BOOLEAN;     (* Payload Unit Start Indicator *)
>     transPrio: BITS 1 FOR [0..1];
>     pid: BITS 13 FOR PID;
>     transScramControl: BITS 2 FOR [0..3]; (* 00 means no scrambling *)
>     afc: BITS 2 FOR [0..3]; (* 01 - no adaptation field, payload only *)
>     cc: BITS 4 FOR Nibble;
>   END;
> 
> My data, pusi is TRUE, sync is 0x47, pid is 4129 (0x1021), cc is 5 and afc is 0x1.Rest is zeros.
> 
> What I get is:
> 
> 0000 1010 1000 0001 0101 0100
> 
> last five bits of pid; one bit for transPrio, one bit for pusi (TRUE), one bit for tErrInd;
> first eight bits of pid
> four bits of cc; two bits of abc; two bits for transScramControl
> 
> a mess. with pid being most special sort of it :).
> 
> Is this excected/normal? Wasn't whole idea os packing data into record about packing bits left-right-until-spent?
> 
> TIA,
> dd
> 
 		 	   		  
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