[M3devel] turning off checking?
mika at async.caltech.edu
mika at async.caltech.edu
Thu Jul 24 12:08:33 CEST 2014
I added M3_OPTIONS=["NoChecks"] to my cm3.cfg:
(62)truffles:~/t/btc/hsim/gcrit/src>cm3 -x
--- building in ../AMD64_LINUX ---
new source -> compiling CardCritAttrTbl.i3
m3c: unknown option, "NoChecks"
Fatal Error: failed compiling:
I know my inner loops are littered with "CheckLoadTracedRef"...
For fun, here is an example:
389 VAR p := min.priority;
390 s := min.node.succ;
391 d := min.node.sDly;
392 BEGIN
393
395 FOR i := 0 TO min.node.ns-1 DO
396 HandleFanout(p, s[i], d[i])
397 END;
398 END;
min is an object (an extended PQ element with priority of LONGREAL)
node is some other object of type Node with succ and sDly being arrays.
succ is a pointer to another Node. sDly is a LONGREAL. ns is used to amortize
reallocations. I think you can guess what this code does (sort of).
Here is the assembly---looks nasty! :
/big/home/mika/t/zpy/hsim/gcrit/AMD64_LINUX/../src/ERS.m3:389
40ad05: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
40ad0c: 48 8b 40 08 mov 0x8(%rax),%rax
40ad10: 48 89 45 90 mov %rax,-0x70(%rbp)
/big/home/mika/t/zpy/hsim/gcrit/AMD64_LINUX/../src/ERS.m3:390
40ad14: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
40ad1b: 48 8b 40 28 mov 0x28(%rax),%rax
40ad1f: 48 89 45 a8 mov %rax,-0x58(%rbp)
40ad23: 48 83 7d a8 00 cmpq $0x0,-0x58(%rbp)
40ad28: 74 34 je 40ad5e <ERS__INext+0x391>
40ad2a: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ad2e: 83 e0 01 and $0x1,%eax
40ad31: 83 e0 01 and $0x1,%eax
40ad34: 84 c0 test %al,%al
40ad36: 75 26 jne 40ad5e <ERS__INext+0x391>
40ad38: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ad3c: 48 83 e8 08 sub $0x8,%rax
40ad40: 48 8b 00 mov (%rax),%rax
40ad43: 48 c1 e0 29 shl $0x29,%rax
40ad47: 48 c1 e8 3f shr $0x3f,%rax
40ad4b: 83 e0 01 and $0x1,%eax
40ad4e: 84 c0 test %al,%al
40ad50: 74 0c je 40ad5e <ERS__INext+0x391>
40ad52: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ad56: 48 89 c7 mov %rax,%rdi
40ad59: e8 4e 0d 0b 00 callq 4bbaac <RTHooks__CheckLoadTracedRef>
40ad5e: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ad62: 48 8b 40 28 mov 0x28(%rax),%rax
40ad66: 48 89 45 a0 mov %rax,-0x60(%rbp)
40ad6a: 48 83 7d a0 00 cmpq $0x0,-0x60(%rbp)
40ad6f: 74 34 je 40ada5 <ERS__INext+0x3d8>
40ad71: 48 8b 45 a0 mov -0x60(%rbp),%rax
40ad75: 83 e0 01 and $0x1,%eax
40ad78: 83 e0 01 and $0x1,%eax
40ad7b: 84 c0 test %al,%al
40ad7d: 75 26 jne 40ada5 <ERS__INext+0x3d8>
40ad7f: 48 8b 45 a0 mov -0x60(%rbp),%rax
40ad83: 48 83 e8 08 sub $0x8,%rax
40ad87: 48 8b 00 mov (%rax),%rax
40ad8a: 48 c1 e0 29 shl $0x29,%rax
40ad8e: 48 c1 e8 3f shr $0x3f,%rax
40ad92: 83 e0 01 and $0x1,%eax
40ad95: 84 c0 test %al,%al
40ad97: 74 0c je 40ada5 <ERS__INext+0x3d8>
40ad99: 48 8b 45 a0 mov -0x60(%rbp),%rax
40ad9d: 48 89 c7 mov %rax,%rdi
40ada0: e8 07 0d 0b 00 callq 4bbaac <RTHooks__CheckLoadTracedRef>
40ada5: 48 8b 45 a0 mov -0x60(%rbp),%rax
40ada9: 48 89 45 88 mov %rax,-0x78(%rbp)
/big/home/mika/t/zpy/hsim/gcrit/AMD64_LINUX/../src/ERS.m3:391
40adad: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
40adb4: 48 8b 40 28 mov 0x28(%rax),%rax
40adb8: 48 89 45 a0 mov %rax,-0x60(%rbp)
40adbc: 48 83 7d a0 00 cmpq $0x0,-0x60(%rbp)
40adc1: 74 34 je 40adf7 <ERS__INext+0x42a>
40adc3: 48 8b 45 a0 mov -0x60(%rbp),%rax
40adc7: 83 e0 01 and $0x1,%eax
40adca: 83 e0 01 and $0x1,%eax
40adcd: 84 c0 test %al,%al
40adcf: 75 26 jne 40adf7 <ERS__INext+0x42a>
40add1: 48 8b 45 a0 mov -0x60(%rbp),%rax
40add5: 48 83 e8 08 sub $0x8,%rax
40add9: 48 8b 00 mov (%rax),%rax
40addc: 48 c1 e0 29 shl $0x29,%rax
40ade0: 48 c1 e8 3f shr $0x3f,%rax
40ade4: 83 e0 01 and $0x1,%eax
40ade7: 84 c0 test %al,%al
40ade9: 74 0c je 40adf7 <ERS__INext+0x42a>
40adeb: 48 8b 45 a0 mov -0x60(%rbp),%rax
40adef: 48 89 c7 mov %rax,%rdi
40adf2: e8 b5 0c 0b 00 callq 4bbaac <RTHooks__CheckLoadTracedRef>
40adf7: 48 8b 45 a0 mov -0x60(%rbp),%rax
40adfb: 48 8b 40 30 mov 0x30(%rax),%rax
40adff: 48 89 45 a8 mov %rax,-0x58(%rbp)
40ae03: 48 83 7d a8 00 cmpq $0x0,-0x58(%rbp)
40ae08: 74 34 je 40ae3e <ERS__INext+0x471>
40ae0a: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ae0e: 83 e0 01 and $0x1,%eax
40ae11: 83 e0 01 and $0x1,%eax
40ae14: 84 c0 test %al,%al
40ae16: 75 26 jne 40ae3e <ERS__INext+0x471>
40ae18: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ae1c: 48 83 e8 08 sub $0x8,%rax
40ae20: 48 8b 00 mov (%rax),%rax
40ae23: 48 c1 e0 29 shl $0x29,%rax
40ae27: 48 c1 e8 3f shr $0x3f,%rax
40ae2b: 83 e0 01 and $0x1,%eax
40ae2e: 84 c0 test %al,%al
40ae30: 74 0c je 40ae3e <ERS__INext+0x471>
40ae32: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ae36: 48 89 c7 mov %rax,%rdi
40ae39: e8 6e 0c 0b 00 callq 4bbaac <RTHooks__CheckLoadTracedRef>
40ae3e: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ae42: 48 89 45 80 mov %rax,-0x80(%rbp)
/big/home/mika/t/zpy/hsim/gcrit/AMD64_LINUX/../src/ERS.m3:394
40ae46: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
40ae4d: 48 8b 40 28 mov 0x28(%rax),%rax
40ae51: 48 89 45 a8 mov %rax,-0x58(%rbp)
40ae55: 48 83 7d a8 00 cmpq $0x0,-0x58(%rbp)
40ae5a: 74 34 je 40ae90 <ERS__INext+0x4c3>
40ae5c: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ae60: 83 e0 01 and $0x1,%eax
40ae63: 83 e0 01 and $0x1,%eax
40ae66: 84 c0 test %al,%al
40ae68: 75 26 jne 40ae90 <ERS__INext+0x4c3>
40ae6a: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ae6e: 48 83 e8 08 sub $0x8,%rax
40ae72: 48 8b 00 mov (%rax),%rax
40ae75: 48 c1 e0 29 shl $0x29,%rax
40ae79: 48 c1 e8 3f shr $0x3f,%rax
40ae7d: 83 e0 01 and $0x1,%eax
40ae80: 84 c0 test %al,%al
40ae82: 74 0c je 40ae90 <ERS__INext+0x4c3>
40ae84: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ae88: 48 89 c7 mov %rax,%rdi
40ae8b: e8 1c 0c 0b 00 callq 4bbaac <RTHooks__CheckLoadTracedRef>
40ae90: 48 8b 45 a8 mov -0x58(%rbp),%rax
40ae94: 48 83 c0 20 add $0x20,%rax
40ae98: 48 8b 00 mov (%rax),%rax
40ae9b: 48 83 e8 01 sub $0x1,%rax
40ae9f: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp)
40aea6: 48 c7 45 c8 00 00 00 movq $0x0,-0x38(%rbp)
40aead: 00
40aeae: 48 8b 85 78 ff ff ff mov -0x88(%rbp),%rax
40aeb5: 48 89 85 70 ff ff ff mov %rax,-0x90(%rbp)
40aebc: e9 f2 00 00 00 jmpq 40afb3 <ERS__INext+0x5e6>
/big/home/mika/t/zpy/hsim/gcrit/AMD64_LINUX/../src/ERS.m3:395
40aec1: 48 8b 45 88 mov -0x78(%rbp),%rax
40aec5: 48 89 45 a8 mov %rax,-0x58(%rbp)
40aec9: 48 8b 55 c8 mov -0x38(%rbp),%rdx
40aecd: 48 8b 45 a8 mov -0x58(%rbp),%rax
40aed1: 48 83 c0 08 add $0x8,%rax
40aed5: 48 8b 00 mov (%rax),%rax
40aed8: 48 39 c2 cmp %rax,%rdx
40aedb: 72 0a jb 40aee7 <ERS__INext+0x51a>
40aedd: bf 62 31 00 00 mov $0x3162,%edi
40aee2: e8 50 0c 00 00 callq 40bb37 <_m3_fault>
40aee7: 48 8b 45 a8 mov -0x58(%rbp),%rax
40aeeb: 48 8b 10 mov (%rax),%rdx
40aeee: 48 8b 45 c8 mov -0x38(%rbp),%rax
40aef2: 48 c1 e0 03 shl $0x3,%rax
40aef6: 48 01 d0 add %rdx,%rax
40aef9: 48 8b 00 mov (%rax),%rax
40aefc: 48 89 45 a0 mov %rax,-0x60(%rbp)
40af00: 48 83 7d a0 00 cmpq $0x0,-0x60(%rbp)
40af05: 74 34 je 40af3b <ERS__INext+0x56e>
40af07: 48 8b 45 a0 mov -0x60(%rbp),%rax
40af0b: 83 e0 01 and $0x1,%eax
40af0e: 83 e0 01 and $0x1,%eax
40af11: 84 c0 test %al,%al
40af13: 75 26 jne 40af3b <ERS__INext+0x56e>
40af15: 48 8b 45 a0 mov -0x60(%rbp),%rax
40af19: 48 83 e8 08 sub $0x8,%rax
40af1d: 48 8b 00 mov (%rax),%rax
40af20: 48 c1 e0 29 shl $0x29,%rax
40af24: 48 c1 e8 3f shr $0x3f,%rax
40af28: 83 e0 01 and $0x1,%eax
40af2b: 84 c0 test %al,%al
40af2d: 74 0c je 40af3b <ERS__INext+0x56e>
40af2f: 48 8b 45 a0 mov -0x60(%rbp),%rax
40af33: 48 89 c7 mov %rax,%rdi
40af36: e8 71 0b 0b 00 callq 4bbaac <RTHooks__CheckLoadTracedRef>
40af3b: 48 8b 45 80 mov -0x80(%rbp),%rax
40af3f: 48 89 45 98 mov %rax,-0x68(%rbp)
40af43: 48 8b 55 c8 mov -0x38(%rbp),%rdx
40af47: 48 8b 45 98 mov -0x68(%rbp),%rax
40af4b: 48 83 c0 08 add $0x8,%rax
40af4f: 48 8b 00 mov (%rax),%rax
40af52: 48 39 c2 cmp %rax,%rdx
40af55: 72 0a jb 40af61 <ERS__INext+0x594>
40af57: bf 62 31 00 00 mov $0x3162,%edi
40af5c: e8 d6 0b 00 00 callq 40bb37 <_m3_fault>
40af61: 48 8b 45 98 mov -0x68(%rbp),%rax
40af65: 48 8b 10 mov (%rax),%rdx
40af68: 48 8b 45 c8 mov -0x38(%rbp),%rax
40af6c: 48 c1 e0 03 shl $0x3,%rax
40af70: 48 01 d0 add %rdx,%rax
40af73: 48 8b 10 mov (%rax),%rdx
40af76: 48 8b 4d a0 mov -0x60(%rbp),%rcx
40af7a: 48 8b 45 90 mov -0x70(%rbp),%rax
40af7e: 48 8d b5 30 ff ff ff lea -0xd0(%rbp),%rsi
40af85: 49 89 f2 mov %rsi,%r10
40af88: 48 89 95 18 ff ff ff mov %rdx,-0xe8(%rbp)
40af8f: f2 0f 10 8d 18 ff ff movsd -0xe8(%rbp),%xmm1
40af96: ff
40af97: 48 89 cf mov %rcx,%rdi
40af9a: 48 89 85 18 ff ff ff mov %rax,-0xe8(%rbp)
40afa1: f2 0f 10 85 18 ff ff movsd -0xe8(%rbp),%xmm0
40afa8: ff
40afa9: e8 15 f3 ff ff callq 40a2c3 <ERS__INext__HandleFanout.1183>
/big/home/mika/t/zpy/hsim/gcrit/AMD64_LINUX/../src/ERS.m3:394
40afae: 48 83 45 c8 01 addq $0x1,-0x38(%rbp)
40afb3: 48 8b 85 70 ff ff ff mov -0x90(%rbp),%rax
40afba: 48 3b 45 c8 cmp -0x38(%rbp),%rax
40afbe: 0f 8d fd fe ff ff jge 40aec1 <ERS__INext+0x4f4>
Antony Hosking writes:
>Looks like -D=92M3_OPTIONS=3D["NoChecks"]=92
>
>On Jul 23, 2014, at 12:41 PM, mika at async.caltech.edu wrote:
>
>>=20
>> Thanks Tony... but now I am at the same question as the authors of =
>that
>> email exchange. How to get the option to that block of code?? Hmm...
>>=20
>> Antony Hosking writes:
>>> Hmm, I knew once how to do this. Let me see=3D85
>>>=20
>>> Here is a link that suggests how: =3D
>>> =
>https://mail.elegosoft.com/pipermail/m3devel/2007-November/000634.html
>>>=20
>>>=20
>>> On Jul 23, 2014, at 6:45 AM, mika at async.caltech.edu wrote:
>>>=20
>>>> Hi m3devel,
>>>> =3D20
>>>> Does anyone remember how to turn off...
>>>> =3D20
>>>> -- bounds checking
>>>> =3D20
>>>> -- NIL checking
>>>> =3D20
>>>> -- etc....
>>>> =3D20
>>>> Mika
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